| Author |
Sony xperia 1 mark 5 announced |
Hawk12
Joined: Nov 29, 2018
Posts: > 500
PM |
On 2023-06-13 15:20:44, RacSony wrote:
Xperia 1 V is definitely the best, but am I the only one who thinks the original Xperia 1 is the second best?
https://sumahodigest.com/?p=20795
whoever took that photo, should have edit to correct WB.
No way purple iii has that shade, purple iii is cheap grape juice purple.
the photo has made it look like purple mark 1.
I want mix of both, flat glass + centered camera. | |
|
tai020381
Joined: Dec 07, 2004
Posts: > 500
PM |
Android 14
https://youtu.be/scCDjWG8mNk |
Hawk12
Joined: Nov 29, 2018
Posts: > 500
PM |
update to android 15 + security up to mid 2026 |
McKinley
Joined: Feb 23, 2004
Posts: > 500
From: Sweden, USA Los Angeles CA
PM |
In Sweden, one of the main ISP offers Sony Xperia 1V with WH-1000XM5.
An Old Sony fan as I am, I had a hard time to pass on this offer.
So the 4th of July is going to be the day when I will share my findings with you.
 GH688, T28, T39 and T68 Nokia 6110, 8110, 8850, 6230, N82 Moto V525 and RAZR V3 Samsung T100, S300 and E700  T68, T610, Z600, T630, K700, S700, V800, K750, S600, M600, S500, P1i, K850, X1 X10, Vivaz |
Hawk12
Joined: Nov 29, 2018
Posts: > 500
PM |
On 2023-06-14 18:13:14, McKinley wrote:
In Sweden, one of the main ISP offers Sony Xperia 1V with WH-1000XM5.
An Old Sony fan as I am, I had a hard time to pass on this offer.
So the 4th of July is going to be the day when I will share my findings with you.
If you do not mind the ufs3.1 by sk hynix when it should have ufs4.0 from samsung or micron. |
xpr
Joined: May 23, 2018
Posts: 326
From: Israel
PM |
On 2023-06-14 19:03:06, Hawk12 wrote:
On 2023-06-14 18:13:14, McKinley wrote:
In Sweden, one of the main ISP offers Sony Xperia 1V with WH-1000XM5.
An Old Sony fan as I am, I had a hard time to pass on this offer.
So the 4th of July is going to be the day when I will share my findings with you.
If you do not mind the ufs3.1 by sk hynix when it should have ufs4.0 from samsung or micron.
Are all EU models with 3.1? |
Hawk12
Joined: Nov 29, 2018
Posts: > 500
PM |
On 2023-06-14 21:42:55, xpr wrote:
On 2023-06-14 19:03:06, Hawk12 wrote:
On 2023-06-14 18:13:14, McKinley wrote:
In Sweden, one of the main ISP offers Sony Xperia 1V with WH-1000XM5.
An Old Sony fan as I am, I had a hard time to pass on this offer.
So the 4th of July is going to be the day when I will share my findings with you.
If you do not mind the ufs3.1 by sk hynix when it should have ufs4.0 from samsung or micron.
Are all EU models with 3.1?
The chinese variant is 3.1 ... I have no idea if there is any with 4.0
|
RacSony
Joined: Mar 24, 2017
Posts: > 500
PM |
On 2023-06-15 00:23:38, Hawk12 wrote:
On 2023-06-14 21:42:55, xpr wrote:
On 2023-06-14 19:03:06, Hawk12 wrote:
On 2023-06-14 18:13:14, McKinley wrote:
In Sweden, one of the main ISP offers Sony Xperia 1V with WH-1000XM5.
An Old Sony fan as I am, I had a hard time to pass on this offer.
So the 4th of July is going to be the day when I will share my findings with you.
If you do not mind the ufs3.1 by sk hynix when it should have ufs4.0 from samsung or micron.
Are all EU models with 3.1?
The chinese variant is 3.1 ... I have no idea if there is any with 4.0
How did you know? |
tai020381
Joined: Dec 07, 2004
Posts: > 500
PM |
On 2023-06-15 00:23:38, Hawk12 wrote:
On 2023-06-14 21:42:55, xpr wrote:
On 2023-06-14 19:03:06, Hawk12 wrote:
On 2023-06-14 18:13:14, McKinley wrote:
In Sweden, one of the main ISP offers Sony Xperia 1V with WH-1000XM5.
An Old Sony fan as I am, I had a hard time to pass on this offer.
So the 4th of July is going to be the day when I will share my findings with you.
If you do not mind the ufs3.1 by sk hynix when it should have ufs4.0 from samsung or micron.
Are all EU models with 3.1?
The chinese variant is 3.1 ... I have no idea if there is any with 4.0
If it's 3.1 and during speed test comparison can win samsung s23 ultra with UFS 4.0 that will be a real feat already haha 
[ This Message was edited by: tai020381 on 2023-06-15 08:44 ] |
Hawk12
Joined: Nov 29, 2018
Posts: > 500
PM |
On 2023-06-15 01:18:25, RacSony wrote:
On 2023-06-15 00:23:38, Hawk12 wrote:
On 2023-06-14 21:42:55, xpr wrote:
On 2023-06-14 19:03:06, Hawk12 wrote:
On 2023-06-14 18:13:14, McKinley wrote:
In Sweden, one of the main ISP offers Sony Xperia 1V with WH-1000XM5.
An Old Sony fan as I am, I had a hard time to pass on this offer.
So the 4th of July is going to be the day when I will share my findings with you.
If you do not mind the ufs3.1 by sk hynix when it should have ufs4.0 from samsung or micron.
Are all EU models with 3.1?
The chinese variant is 3.1 ... I have no idea if there is any with 4.0
How did you know?
https://m.weibo.cn/detail/4912633592155442
Looks like Sony Semi ismgonna change name scheme for exmor.
Imx888 would be LYT800. It is actually 53MP 1.12 micron , 11.2mm diagonal.
[ This Message was edited by: Hawk12 on 2023-06-15 10:13 ] |
Hawk12
Joined: Nov 29, 2018
Posts: > 500
PM |
Image Sensors World reprinted the Exmor T IMX888 53Mp 1/1.35 1.12um Dual Photodio adopted by TechInsights for SONY XQ-DQ72 Pixel process analysis of de AF CMOS Image Sensor.
This article was written by TechInsights image sensor experts: Eric Rutulis and Dr. John Scott-Thomas:
We first heard of it (double-layer transistor) on IEDM in 2021, and Sony provided more details at the IEEE VLSI technology and circuit seminar in 2022. Now that it is on the market, TechInsights has seen the world's first double-layer transistor image sensor for the first time. Here we introduce our preliminary results. The device was found in the main camera of the Sony Xperia 1V smartphone, with a pixel spacing of 48 million pixels and 1.12 microns. We can confirm that it has dual photodiodes (the left and right photodiodes in each pixel are used for full array PDAF). The chip size is 11.37 x 7.69 mm, from edge to edge.
In fact, the sensor actually has three layers of active silicon, and the image signal processor (ISP) uses the direct bonding interface (DBI) to stack to the "second layer" (which we will use Sony's nomenclature as much as possible) CMOS image sensor (CIS). Figure 1 shows the SEM cross-section of the array. Light enters from the bottom of the image through microlens and color filters. Each pixel is separated by a raster (with a composite layer) to improve quantum efficiency. Front deep groove isolation is used between each photodiode, and Sony seems to use silica in deep grooves to improve full well capacity and quantum efficiency (this will be confirmed by further analysis). The layer also has a plane transmission gate for transferring the photoelectric charge from the diode to the floating diffusion region. Above the first layer is the "second layer" of silicon, each pixel contains three transistors; reset, amplifier (source follower) and select transistor. These transistors are located above the second layer of silicon and use "deep contact" to achieve a connection with the first layer, which passes through the second layer and basically forms a silicon through hole (TSV). Finally, the ISP is located on the metallization of the second layer, using mixed (direct) bonding to connect. The copper wire used to connect the ISP to CIS DBI Cu is not visible in this image.
The key to this structure is a process, which can withstand the thermal cycle required to create thermal oxides and activate the injection on the second layer. Sony described the process in detail (IEDM 2021, "3D sequential process integration of CMOS image sensor").
Figure 2 is an image from this article, showing the process. The first layer of photodiode and transmission gate is formed, and the second layer is wafer bonded and thinned. Only in this way can a second layer of gate oxide be formed and the injection can be activated. Finally, deep contact is formed, etching passes through the second layer and contacts the first layer of the device.
Figure 3 shows the interface between the first layer and the second layer in more detail. The transmission gate (TG in the figure) is connected to the first metal layer of the second layer. The slightly longer deep contact is located below the surface of the sample and is partially visible in the image. They connect the floating diffusion nodes between the first and second layers. Sub-local connection (below the sample surface) is used to interconnect the four photodiodes above the first layer to the source of the reset FET and the gate of the AMP (source follower) FET.
Figure 4 discusses the sub-local connection in detail. This is the plane SEM image of the first layer of the bottom layer. The yellow box outlines the pixel outline, and PDL and PDR represent the left and right photodiodes. One microlens covers each pixel. It indicates the sub-local connection, which is used to interconnect the floating diffusion of two pixels and the grounding of four pixels. The near-local connection seems to be polysilicon; this is currently being confirmed by further analysis.
The motivation of the double-layer structure is multifaceted. Even if the pixel spacing is reduced, the full well capacity of the photodiode can be maintained. The use of sub-local contact reduces the capacitance of floating diffusion and increases the conversion gain of pixels. The increased usable area on the second layer allows to increase the AMP (source follower) transistor area, thus reducing the noise (flickering and telegraph) generated in the device channel.
It's worth taking some time to appreciate Sony's achievements here. The new process and deep contact technology allow two layers of active devices to interconnect with an impressive 0.46 µm (center to center) deep contact (or silicon through-hole) spacing. Even the mixed bond with ISP is only 1.12 µm; the minimum pitch seen by TechInsights so far. At the recent International Image Sensor Symposium, Sony described the next generation, which will use the embedded "embedded" sub-local connection embedded in the first layer and the pixel FinFets (coming soon) of the second layer. Perhaps we are seeing the first stage of a real 3D circuit, where the active devices on multi-layer silicon are connected to each other. |
xpr
Joined: May 23, 2018
Posts: 326
From: Israel
PM |
On 2023-06-18 01:22:43, Hawk12 wrote:
Image Sensors World reprinted the Exmor T IMX888 53Mp 1/1.35 1.12um Dual Photodio adopted by TechInsights for SONY XQ-DQ72 Pixel process analysis of de AF CMOS Image Sensor.
This article was written by TechInsights image sensor experts: Eric Rutulis and Dr. John Scott-Thomas:
We first heard of it (double-layer transistor) on IEDM in 2021, and Sony provided more details at the IEEE VLSI technology and circuit seminar in 2022. Now that it is on the market, TechInsights has seen the world's first double-layer transistor image sensor for the first time. Here we introduce our preliminary results. The device was found in the main camera of the Sony Xperia 1V smartphone, with a pixel spacing of 48 million pixels and 1.12 microns. We can confirm that it has dual photodiodes (the left and right photodiodes in each pixel are used for full array PDAF). The chip size is 11.37 x 7.69 mm, from edge to edge.
In fact, the sensor actually has three layers of active silicon, and the image signal processor (ISP) uses the direct bonding interface (DBI) to stack to the "second layer" (which we will use Sony's nomenclature as much as possible) CMOS image sensor (CIS). Figure 1 shows the SEM cross-section of the array. Light enters from the bottom of the image through microlens and color filters. Each pixel is separated by a raster (with a composite layer) to improve quantum efficiency. Front deep groove isolation is used between each photodiode, and Sony seems to use silica in deep grooves to improve full well capacity and quantum efficiency (this will be confirmed by further analysis). The layer also has a plane transmission gate for transferring the photoelectric charge from the diode to the floating diffusion region. Above the first layer is the "second layer" of silicon, each pixel contains three transistors; reset, amplifier (source follower) and select transistor. These transistors are located above the second layer of silicon and use "deep contact" to achieve a connection with the first layer, which passes through the second layer and basically forms a silicon through hole (TSV). Finally, the ISP is located on the metallization of the second layer, using mixed (direct) bonding to connect. The copper wire used to connect the ISP to CIS DBI Cu is not visible in this image.
The key to this structure is a process, which can withstand the thermal cycle required to create thermal oxides and activate the injection on the second layer. Sony described the process in detail (IEDM 2021, "3D sequential process integration of CMOS image sensor").
Figure 2 is an image from this article, showing the process. The first layer of photodiode and transmission gate is formed, and the second layer is wafer bonded and thinned. Only in this way can a second layer of gate oxide be formed and the injection can be activated. Finally, deep contact is formed, etching passes through the second layer and contacts the first layer of the device.
Figure 3 shows the interface between the first layer and the second layer in more detail. The transmission gate (TG in the figure) is connected to the first metal layer of the second layer. The slightly longer deep contact is located below the surface of the sample and is partially visible in the image. They connect the floating diffusion nodes between the first and second layers. Sub-local connection (below the sample surface) is used to interconnect the four photodiodes above the first layer to the source of the reset FET and the gate of the AMP (source follower) FET.
Figure 4 discusses the sub-local connection in detail. This is the plane SEM image of the first layer of the bottom layer. The yellow box outlines the pixel outline, and PDL and PDR represent the left and right photodiodes. One microlens covers each pixel. It indicates the sub-local connection, which is used to interconnect the floating diffusion of two pixels and the grounding of four pixels. The near-local connection seems to be polysilicon; this is currently being confirmed by further analysis.
The motivation of the double-layer structure is multifaceted. Even if the pixel spacing is reduced, the full well capacity of the photodiode can be maintained. The use of sub-local contact reduces the capacitance of floating diffusion and increases the conversion gain of pixels. The increased usable area on the second layer allows to increase the AMP (source follower) transistor area, thus reducing the noise (flickering and telegraph) generated in the device channel.
It's worth taking some time to appreciate Sony's achievements here. The new process and deep contact technology allow two layers of active devices to interconnect with an impressive 0.46 µm (center to center) deep contact (or silicon through-hole) spacing. Even the mixed bond with ISP is only 1.12 µm; the minimum pitch seen by TechInsights so far. At the recent International Image Sensor Symposium, Sony described the next generation, which will use the embedded "embedded" sub-local connection embedded in the first layer and the pixel FinFets (coming soon) of the second layer. Perhaps we are seeing the first stage of a real 3D circuit, where the active devices on multi-layer silicon are connected to each other.
Could you share the original article? |
Hawk12
Joined: Nov 29, 2018
Posts: > 500
PM |
On 2023-06-18 10:28:31, xpr wrote:
On 2023-06-18 01:22:43, Hawk12 wrote:
Image Sensors World reprinted the Exmor T IMX888 53Mp 1/1.35 1.12um Dual Photodio adopted by TechInsights for SONY XQ-DQ72 Pixel process analysis of de AF CMOS Image Sensor.
This article was written by TechInsights image sensor experts: Eric Rutulis and Dr. John Scott-Thomas:
We first heard of it (double-layer transistor) on IEDM in 2021, and Sony provided more details at the IEEE VLSI technology and circuit seminar in 2022. Now that it is on the market, TechInsights has seen the world's first double-layer transistor image sensor for the first time. Here we introduce our preliminary results. The device was found in the main camera of the Sony Xperia 1V smartphone, with a pixel spacing of 48 million pixels and 1.12 microns. We can confirm that it has dual photodiodes (the left and right photodiodes in each pixel are used for full array PDAF). The chip size is 11.37 x 7.69 mm, from edge to edge.
In fact, the sensor actually has three layers of active silicon, and the image signal processor (ISP) uses the direct bonding interface (DBI) to stack to the "second layer" (which we will use Sony's nomenclature as much as possible) CMOS image sensor (CIS). Figure 1 shows the SEM cross-section of the array. Light enters from the bottom of the image through microlens and color filters. Each pixel is separated by a raster (with a composite layer) to improve quantum efficiency. Front deep groove isolation is used between each photodiode, and Sony seems to use silica in deep grooves to improve full well capacity and quantum efficiency (this will be confirmed by further analysis). The layer also has a plane transmission gate for transferring the photoelectric charge from the diode to the floating diffusion region. Above the first layer is the "second layer" of silicon, each pixel contains three transistors; reset, amplifier (source follower) and select transistor. These transistors are located above the second layer of silicon and use "deep contact" to achieve a connection with the first layer, which passes through the second layer and basically forms a silicon through hole (TSV). Finally, the ISP is located on the metallization of the second layer, using mixed (direct) bonding to connect. The copper wire used to connect the ISP to CIS DBI Cu is not visible in this image.
The key to this structure is a process, which can withstand the thermal cycle required to create thermal oxides and activate the injection on the second layer. Sony described the process in detail (IEDM 2021, "3D sequential process integration of CMOS image sensor").
Figure 2 is an image from this article, showing the process. The first layer of photodiode and transmission gate is formed, and the second layer is wafer bonded and thinned. Only in this way can a second layer of gate oxide be formed and the injection can be activated. Finally, deep contact is formed, etching passes through the second layer and contacts the first layer of the device.
Figure 3 shows the interface between the first layer and the second layer in more detail. The transmission gate (TG in the figure) is connected to the first metal layer of the second layer. The slightly longer deep contact is located below the surface of the sample and is partially visible in the image. They connect the floating diffusion nodes between the first and second layers. Sub-local connection (below the sample surface) is used to interconnect the four photodiodes above the first layer to the source of the reset FET and the gate of the AMP (source follower) FET.
Figure 4 discusses the sub-local connection in detail. This is the plane SEM image of the first layer of the bottom layer. The yellow box outlines the pixel outline, and PDL and PDR represent the left and right photodiodes. One microlens covers each pixel. It indicates the sub-local connection, which is used to interconnect the floating diffusion of two pixels and the grounding of four pixels. The near-local connection seems to be polysilicon; this is currently being confirmed by further analysis.
The motivation of the double-layer structure is multifaceted. Even if the pixel spacing is reduced, the full well capacity of the photodiode can be maintained. The use of sub-local contact reduces the capacitance of floating diffusion and increases the conversion gain of pixels. The increased usable area on the second layer allows to increase the AMP (source follower) transistor area, thus reducing the noise (flickering and telegraph) generated in the device channel.
It's worth taking some time to appreciate Sony's achievements here. The new process and deep contact technology allow two layers of active devices to interconnect with an impressive 0.46 µm (center to center) deep contact (or silicon through-hole) spacing. Even the mixed bond with ISP is only 1.12 µm; the minimum pitch seen by TechInsights so far. At the recent International Image Sensor Symposium, Sony described the next generation, which will use the embedded "embedded" sub-local connection embedded in the first layer and the pixel FinFets (coming soon) of the second layer. Perhaps we are seeing the first stage of a real 3D circuit, where the active devices on multi-layer silicon are connected to each other.
Could you share the original article?
got this from weibo ... I just crtled c + crtled v it |
lewisken02
Joined: Feb 22, 2018
Posts: 23
PM |
On 2023-06-18 10:28:31, xpr wrote:
On 2023-06-18 01:22:43, Hawk12 wrote:
Image Sensors World reprinted the Exmor T IMX888 53Mp 1/1.35 1.12um Dual Photodio adopted by TechInsights for SONY XQ-DQ72 Pixel process analysis of de AF CMOS Image Sensor.
This article was written by TechInsights image sensor experts: Eric Rutulis and Dr. John Scott-Thomas:
We first heard of it (double-layer transistor) on IEDM in 2021, and Sony provided more details at the IEEE VLSI technology and circuit seminar in 2022. Now that it is on the market, TechInsights has seen the world's first double-layer transistor image sensor for the first time. Here we introduce our preliminary results. The device was found in the main camera of the Sony Xperia 1V smartphone, with a pixel spacing of 48 million pixels and 1.12 microns. We can confirm that it has dual photodiodes (the left and right photodiodes in each pixel are used for full array PDAF). The chip size is 11.37 x 7.69 mm, from edge to edge.
In fact, the sensor actually has three layers of active silicon, and the image signal processor (ISP) uses the direct bonding interface (DBI) to stack to the "second layer" (which we will use Sony's nomenclature as much as possible) CMOS image sensor (CIS). Figure 1 shows the SEM cross-section of the array. Light enters from the bottom of the image through microlens and color filters. Each pixel is separated by a raster (with a composite layer) to improve quantum efficiency. Front deep groove isolation is used between each photodiode, and Sony seems to use silica in deep grooves to improve full well capacity and quantum efficiency (this will be confirmed by further analysis). The layer also has a plane transmission gate for transferring the photoelectric charge from the diode to the floating diffusion region. Above the first layer is the "second layer" of silicon, each pixel contains three transistors; reset, amplifier (source follower) and select transistor. These transistors are located above the second layer of silicon and use "deep contact" to achieve a connection with the first layer, which passes through the second layer and basically forms a silicon through hole (TSV). Finally, the ISP is located on the metallization of the second layer, using mixed (direct) bonding to connect. The copper wire used to connect the ISP to CIS DBI Cu is not visible in this image.
The key to this structure is a process, which can withstand the thermal cycle required to create thermal oxides and activate the injection on the second layer. Sony described the process in detail (IEDM 2021, "3D sequential process integration of CMOS image sensor").
Figure 2 is an image from this article, showing the process. The first layer of photodiode and transmission gate is formed, and the second layer is wafer bonded and thinned. Only in this way can a second layer of gate oxide be formed and the injection can be activated. Finally, deep contact is formed, etching passes through the second layer and contacts the first layer of the device.
Figure 3 shows the interface between the first layer and the second layer in more detail. The transmission gate (TG in the figure) is connected to the first metal layer of the second layer. The slightly longer deep contact is located below the surface of the sample and is partially visible in the image. They connect the floating diffusion nodes between the first and second layers. Sub-local connection (below the sample surface) is used to interconnect the four photodiodes above the first layer to the source of the reset FET and the gate of the AMP (source follower) FET.
Figure 4 discusses the sub-local connection in detail. This is the plane SEM image of the first layer of the bottom layer. The yellow box outlines the pixel outline, and PDL and PDR represent the left and right photodiodes. One microlens covers each pixel. It indicates the sub-local connection, which is used to interconnect the floating diffusion of two pixels and the grounding of four pixels. The near-local connection seems to be polysilicon; this is currently being confirmed by further analysis.
The motivation of the double-layer structure is multifaceted. Even if the pixel spacing is reduced, the full well capacity of the photodiode can be maintained. The use of sub-local contact reduces the capacitance of floating diffusion and increases the conversion gain of pixels. The increased usable area on the second layer allows to increase the AMP (source follower) transistor area, thus reducing the noise (flickering and telegraph) generated in the device channel.
It's worth taking some time to appreciate Sony's achievements here. The new process and deep contact technology allow two layers of active devices to interconnect with an impressive 0.46 µm (center to center) deep contact (or silicon through-hole) spacing. Even the mixed bond with ISP is only 1.12 µm; the minimum pitch seen by TechInsights so far. At the recent International Image Sensor Symposium, Sony described the next generation, which will use the embedded "embedded" sub-local connection embedded in the first layer and the pixel FinFets (coming soon) of the second layer. Perhaps we are seeing the first stage of a real 3D circuit, where the active devices on multi-layer silicon are connected to each other.
Could you share the original article?
Heres the source |
Hawk12
Joined: Nov 29, 2018
Posts: > 500
PM |
There is video on youtube (Channel is Kai W).
He claim over 4h of 4K@60 and phone only stopped recording because of battery was low.
😱😱😱😱😱😱😱😱 | |
|
Access the forum with a mobile phone via esato.mobi
|
Posted: 2023-06-13 18:57
GH688, T28, T39 and T68
T68, T610, Z600, T630, K700, S700, V800, K750, S600, M600, S500, P1i, K850, X1 X10, Vivaz
